1. Field of the Invention
The present invention relates in general to a semiconductor memory device, and in particular, to an improvement of a semiconductor memory device in which a sufficient capacitor capacity can be ensured even if degree of integration is increased. The present invention also relates to a method of manufacturing such a semiconductor memory device.
2. Description of the Related Art
In recent years, demands for semiconductor memory devices have been rapidly increased owing to remarkable spread of information equipments such as computers. In connection with function, such devices have been demanded that have a large scale storage capacity and can operate at a high speed. In compliance with these demands, technologies have been developed for improving degree of integration, response and reliability of the semiconductor memory devices.
Dynamic random access memories (DRAMs) have been known as a kind of semiconductor memory devices which enable random input and output of storage information. In general, the DRAM is formed of a memory cell array, which is a storage region storing a large number of storage information, and a peripheral circuitry required for external input and output.
FIG. 1 is a block diagram showing a structure of a conventional DRAM. In FIG. 1, a DRAM 1 includes a memory cell array 2 which stores data signals of stored in formation, a row and column address buffer 3 which externally receives an address signal for selecting a memory cell merely forming a storage circuit, a row decoder 4 and a column decoder 5 which decode the address signal to designate the memory cell, a sense refresh amplifier 6 which amplifies and reads the signal stored in the designated memory cell, data-in buffer 7 and a data-out buffer 8 for data input and output, and a clock generator 9 generating a clock signal. The memory cell array 2 which occupies a large area on the semiconductor chip is provided with a plurality of memory cells, which function merely to store the information and are disposed in a matrix form .
FIG. 2 is an equivalent circuit diagram showing memory cells for four bits forming the memory cell array. Each memory cell in the figure is formed of one MOS transistor and one capacitor connected thereto, and thus is of so-called an one-transistor/one-capacitor type. Since the memory cells of this type have a simple structure, the degree of integration of the memory cell array can be increased easily, and they have been widely used in DRAMs of a large capacity.
The memory cell of the DRAM can be classified into several types based on the structure of the capacitor.
FIG. 3 is a cross section of a memory cell having a typical stacked type capacitor in the prior art. Referring to FIG. 3, the memory cell includes one transfer gate transistor and one stacked type capacitor. The transfer transistor includes a pair of source/drain regions 11 formed at a surface of a silicon substrate 10, and gate electrodes (word lines) 12 formed on the surface of the silicon substrate 10 with an insulating layer therebetween. The stacked type capacitor is formed of a lower electrode (storage node) 14, which is extended over the gate electrode 12 and a field isolating film 13, and is connected to one of the source/drain regions 11, a dielectric layer 15 formed on the surface of the lower electrode 14, and an upper electrode (cell plate) 16 formed on the surface of the dielectric layer 15. The upper electrode 16 is covered with an interlayer insulating film 19 disposed on the silicon substrate 10. In the interlayer insulating film 19, there is provided a contact hole 18 through which the surface of the other source/drain region of the transfer gate transistor is exposed. A bit line 17 is connected to the other source/drain region 11 of the transfer gate transistor through the contact hole 18.
FIG. 4 is a plan showing a semiconductor memory device having a cylindrical capacitor, which belongs to another type of DRAM and is disclosed in Japanese Patent Laying-Open No. 02-89869 (1990). FIG. 5 is a cross section taken along line V--V in FIG. 4.
Referring to these figures, a plurality of word lines 12a, 12b, 12c, 12d and 12e are formed on the surface of the silicon substrate 10. Bit lines 21 extend perpendicularly to the word lines 12a, 12b, 12c, 12d and 12e. Memory cells are provided near crossings of the word lines and bit lines.
Each memory cell is formed of one transfer gate transistor 22 and one capacitor 23. The transfer gate transistor 22 includes a pair of source/drain regions 11 formed at the surface of the silicon substrate 10, and the gate electrodes (word lines 12a and 12b) formed on the surface of the silicon substrate 10. The word lines 12a, 12b, 12c and 12d are covered with an insulating layer 24 provided on the silicon substrate 10. In the insulating layer 24, there is provided a contact hole 25 through which one of the source/drain regions 11 is exposed.
Through the contact hole 25, a storage node 26 is connected to one of the source/drain regions 11. The storage node 26 includes a bottom conductive portion 27 and a side wall conductive portion 28. The bottom conductive portion 27 is in contact with one of the source/drain regions 11 through the contact hole 25 and extends along the surface of the insulating layer 24. The side wall conductive portion 28 is continuous with the outer periphery of the bottom conductive portion 27 and extends upwardly therefrom.
The surface of the storage node 26 is covered with a capacitor insulating film 29, and is further covered with a cell plate 30 with the capacitor insulating film 29 therebetween. The cell plate 30 is covered with an interlayer insulating film 31 provided on the silicon substrate 10. On the interlayer insulating film 31, there are provided interconnection layers 32, which are covered with a protection film 33 provided on the silicon substrate 10.
In the cylindrical capacitor having the aforementioned structure, since the storage node 26 has the side wall conductive portion 28 of which surface contributes to the capacitor capacity, the overall capacity of the capacitor is large.
A method of manufacturing the semiconductor memory device shown in FIG. 5 will be described below.
FIGS. 6-20 are fragmentary cross sections of the semiconductor memory device at a series of steps in a process of manufacturing the semiconductor memory device shown in FIG. 5.
Referring to FIG. 6, a field oxide film 13 is formed on the main surface of the silicon substrate 10 by the LOCOS method.
Referring to FIG. 7, a gate insulating film 34 is formed on the surface of the silicon substrate 10, and then, the word lines 12a, 12b, 12c and 12d made of polysilicon are formed thereon. The insulating layers 24 are formed to cover the word lines 12a, 12b, 12c and 12d. Using the word lines 12a, 12b, 12c and 12d covered with the insulating layers 24 as a mask, impurity ions are implanted into the surface of the silicon substrate 10 to form the source/drain regions 11.
Referring to FIG. 8, a layer of metal such as tungsten, molybdenum or titanium having a high melting point is deposited on the surface of the silicon substrate 10 for forming the bit line 17, and is patterned into a predetermined configuration. The layer thus patterned forms the bit line 17 which is in direct contact with one of the source/drain regions 11 of the transfer gate transistor. An insulating layer 35 is formed to cover the surface of the bit line 17.
Referring to FIG. 9, a first polysilicon layer 36 containing impurity introduced thereinto is deposited on the surface of the silicon substrate 10 by the CVD method.
Referring to FIG. 10, an insulating layer 37 made of a silicon oxide film is deposited on the surface of the silicon substrate 10.
Referring to FIG. 11, resist patterns 38 of a predetermined configuration are formed on the surface of the insulating layer 37. As will be seen later, a width w of the resist pattern 38 determines a distance between adjoining capacitors.
Referring to FIG. 12, the insulating layer 37 is selectively etched using the resist patterns 38 as a mask.
Referring to FIGS. 12 and 13, the resist patterns 38 are removed, and then a second polysilicon layer 39 containing impurity introduced thereinto is deposited on the whole surface of the silicon substrate 10 by the CVD method so that the second polysilicon layer 39 covers the side walls and upper end surfaces of the patterned insulating layers 37.
Referring to FIG. 14, a resist 40 is applied to the surface of the silicon substrate 10 so that the resist 40 fully covers the uppermost surfaces of the second polysilicon layer 39.
Referring to FIGS. 14 and 15, the resist 40 is etched back to expose the upper end surfaces of the second polysilicon layer 39.
Referring to FIGS. 15 and 16, the exposed upper end surfaces of the second polysilicon layer 39 are etched. Thereafter, the insulating layers 37 are removed by etching, e.g., with HF liquid.
Referring to FIGS. 16 and 17, anisotropic etching is effected to remove exposed portions 36a of the first polysilicon layer 36 in a self-aligning manner. Thereafter, the resist 40 is removed. Through these steps, the bottom conductive portion 27 and side wall conductive portion 28 of the storage node 26 are formed.
Referring to FIG. 18, the capacitor insulating film 29 made of, e.g., silicon nitride, silicon oxide, tantalum pentaoxide or hafnium oxide is formed on the surface of the storage node 26.
Referring to FIG. 19, the cell plate 30 is formed to cover the outer surface of the storage node 26 with the capacitor insulating film 29 therebetween. The cell plate 30 is made of material such as polysilicon containing impurity introduced thereinto.
Referring to FIG. 20, the interlayer insulating film 31 is formed on the whole surface of the silicon substrate 10 to cover the cell plate 30. The interconnection layers 32 having a predetermined configuration are formed on the interlayer insulating film 31. The protection film 33 covering the interconnection layers 32 is formed on the whole surface of the silicon substrate 10. Through the aforementioned steps, the semiconductor memory device shown in FIG. 5 is completed.
The semiconductor memory device having the cylindrical capacitors have the structure described above and is manufactured by the aforementioned method.
Meanwhile, such a method was recently proposed that, in order to increase the capacitor capacity, projections formed of silicon particles are provided at the surface of the cylindrical storage node so as to increase the surface area of the capacitor (IEDM, Technical Digest, 1992, pp 259-263).
FIG. 21 is a cross section of a semiconductor memory device having a cylindrical capacitor which is manufactured by the method proposed in the above reference.
The prior art shown in FIG. 21 differs from the prior art shown in FIG. 20 in that silicon particles 41 are provided on the outer surface of the storage node 26, the capacitor insulating film 29 is provided on the outer surface of the storage node 26 including the surfaces of the silicon particles 41, and the cell plate 30 is provided on the capacitor insulating film 29.
The semiconductor memory device shown in FIG. 21 is obtained only by an ideal manufacturing process, and has such a problem that a practical manufacturing process cannot produce the silicon particles 41 having a uniform diameter shown in the figure.
This problem will be described below with reference to the drawings.
FIG. 22 is a fragmentary cross section of the semiconductor memory device at a major step in the process of manufacturing the semiconductor memory device shown in FIG. 21.
The step shown in FIG. 22 is carried out between the steps shown in FIGS. 17 and 18.
The silicon particles 41 are formed on the side wall of the storage node 26 in the following manner.
The silicon substrate 10 provided with the storage node 26 is introduced into a pressure-reduced CVD chamber. A temperature of 600.degree. C. and a high vacuum state of not more than 1.times.10-7 Torr are maintained in the CVD chamber. Under there conditions, Si.sub.2 H.sub.6 gas or the like is flowed through the CVD chamber for ten seconds, so that minute cores of the silicon particles 41 of nearly hemispheric shapes are formed on the surfaces of the bottom conductive portion 27 and side wall conductive portion 28 of the storage node 26.
Referring to FIG. 22, the silicon particle generally has a size of 500 to 1000 .ANG.. However, if the surface state of the storage node 26 is uneven or the process condition is not uniform, the density and sizes of the silicon particles 41 fluctuate.
The uneven surface state of the storage node 26 may be caused, for example, if amorphous silicon at the surface of the storage node 26 is partially crystallized, if residue of resist and/or etching residue are present on the surface of the storage node, and if a natural oxide film is formed on the surface of the storage node. The nonuniform process condition may be caused, for example, by variation of the temperature and/or reduction of the vacuum in the CVD process.
If the sizes of the silicon particles 41 are uneven, a following problem is caused if a space between adjoining storage nodes is small in accordance with high density and high degree of integration of elements.
Referring to FIG. 23, the adjoining storage nodes 26, which are spaced by a short distance from each other, may be short-circuited via the silicon particles 41, resulting in bit error.
Even in the case where the short-circuit does not occur, the space between the adjoining storage nodes 26 is reduced by a distance corresponding to the thicknesses of the huge silicon particles 41, so that the capacitor insulating film 29 and cell plate 30 may not completely cover the outer surfaces of the storage nodes 26. This results in reduction of the memory cell characteristics.